A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop

被引:97
作者
Helal, Belal M. [1 ]
Hsu, Chun-Ming [1 ]
Johnson, Kerwin [1 ]
Perrott, Michael H. [1 ]
机构
[1] MIT, Cambridge, MA 02139 USA
关键词
Subharmonic; injection locked oscillator; pulse; PILO; deterministic jitter; reference spur; correlation; correlated double sampling; gated ring oscillator; GRO; time to digital converter; TDC; integer-N; phase locked loop; PLL; NOISE;
D O I
10.1109/JSSC.2009.2015816
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper introduces a pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 mu m integrated circuit with active area of 0.4 mm(2) and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), -63.9 dBc, and 200 fs (peak-to-peak), respectively.
引用
收藏
页码:1391 / 1400
页数:10
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