Reconfigurable modular arithmetic logic unit for high-performance Public-Key cryptosystems

被引：0

作者：

Sakiyama, K. ^{[1
]}

Mentens, N. ^{[1
]}

Batina, L. ^{[1
]}

Preneel, B. ^{[1
]}

Verbauwhede, I. ^{[1
]}

机构：

[1] Katholieke Univ Leuven, ESAT, COSIC, B-3001 Heverlee, Belgium

来源：

RECONFIGURABLE COMPUTING: ARCHITECTURES AND APPLICATIONS | 2006年 / 3985卷

关键词：

Public-Key cryptography (PKC); RSA; Elliptic Curve Cryptography (ECC); FPGA implementation; reconfigurable architecture;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents a reconfigurable hardware architecture for Public-key cryptosystems. By changing the connections of coarse grain Carry-Save Adders (CSAs), the datapath provides a high performance for both RSA and Elliptic Curve Cryptography (ECC). In addition, we introduce another reconfigurability for the flip-flops in order to make the best of hardware resources. The results of FPGA implementation show that better performance is obtained for ECC on the same hardware platform.

引用

页码：347 / 357

页数：11

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