A 10-Bit 210MHz CMOS D/A converter for WLAN

被引：5

作者：

Cho, HH ^{[1
]}

Park, CY ^{[1
]}

Yune, GS ^{[1
]}

Yoon, KS ^{[1
]}

机构：

[1] Inha Univ, Dept Elect Engn, Inchon 402751, South Korea

来源：

PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS | 2004年

关键词：

D O I：

10.1109/APASIC.2004.1349419

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 10-bit 210MHz CMOS current-mode Digital to Analog Converter (DAC) consisting of 6 bit MSB current cell matrix Sub-DAC, 2 bit mSB unary current source Sub-DAC, and 2 bit LSB binary weighting Sub-DAC for Wireless LAN application. A new deglitch circuit is proposed to control a crossing point of signals and minimize a glitch energy. The proposed 10-bit CMOS current mode DAC was designed by a 0.35mum CMOS double-poly four-metal technology. The effective chip area is 5mm(2). The chip measurement results show a converter rate of 210MHz, DNL/INL of+/-0.7LSB/+/-1.1LSB, a glitch energy of 76pV-sec, a SNR of 50dB, a SFDR of 53dB at 200MHz sampling clock and a power dissipation of 83mW at 3.3V.

引用

页码：106 / 109

页数：4

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