Asymmetric gating for reducing leakage current in carbon nanotube field-effect transistors

As continued silicon scaling is becoming increasingly challenging, emerging nanotechnologies such as carbon nanotubes (CNTs) are being explored. However, experimental measurements of CNT Field-Effect Transistors (CNFETs) often exhibit substantial off-state leakage current (I-OFF), resulting in increased leakage power and potential incorrect logic functionality. In this work, we (1) provide insight into a key component of this off-state leakage current and experimentally demonstrate that it stems from gate-induced drain leakage commonly referred to as GIDL, (2) provide an experimentally calibrated model that closely matches our measured results, and (3) demonstrate a path for mitigating GIDL current by engineering CNFET geometries with asymmetric gates: local back-gate CNFETs whose gate overlaps the source but not the drain. We demonstrate experimentally that this approach can reduce off-state leakage current by >60 x at the same bias voltage (implemented across a wide range of scaled CNFETs with gate lengths ranging from >2 mu m to 180 nm). This reduced leakage current due to the asymmetric gates translates to additional energy-efficiency benefits for CNFETs. Thus, this work addresses a key challenge facing CNFET-based electronics (while simultaneously providing additional energy-efficiency benefits) and is applicable to a wide-range of emerging one-dimensional and two-dimensional nanomaterials. Published under license by AIP Publishing.