Hall effect measurements in SiC buried-channel MOS devices

被引：2
作者：
Saks, NS
Ryu, SH
机构：
[1] USN, Res Lab, Washington, DC 20375 USA
[2] Cree Inc, Durham, NC 27703 USA
来源：
SILICON CARBIDE AND RELATED MATERIALS 2003, PRTS 1 AND 2 | 2004年 / 457-460卷
关键词：
SiC; MOS; buried-channel; Hall mobility; inversion layer;
D O I：
10.4028/www.scientific.net/MSF.457-460.1287
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
Present state-of-the-art SiC MOSFETs suffer from low conductance due to poor inversion layer mobility. To improve the conductance, FETs with implanted buried-channel (BC) n-type layers at the SiC/SiO2 interface are being investigated. In this paper, electron conduction in these implanted BC layers is characterized using the Hall effect. When the FET is biased strongly ON, electron conduction occurs simultaneously in both the n-buried-channel and a surface accumulation layer. These two layers have quite different mobilities which complicates the Hall analysis. Here we describe an approach to analyze the Hall data in order to obtain a correct value for the mobility in the surface accumulation layer of the BC device. Results are compared between BC and surface-channel (SC) devices.
引用
收藏
页码：1287 / 1292
页数：6
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