A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs

被引:29
作者
Kim, Hyun-Sik [1 ]
Yang, Jun-Hyeok [2 ]
Park, Sang-Hui [1 ]
Ryu, Seung-Tak [1 ]
Cho, Gyu-Hyeong [1 ]
机构
[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea
[2] Samsung Elect Co Ltd, Syst LSI Business, Yongin, South Korea
基金
新加坡国家研究基金会;
关键词
Capacitor-string; column driver; digital-to-analog converter (DAC); display driver; iterative charge-sharing based (ICSB); liquid crystal display (LCD); switched-capacitor; voltage interpolation; OPERATIONAL-AMPLIFIER; DAC ARCHITECTURE; POWER;
D O I
10.1109/JSSC.2014.2302301
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a 10-bit column driver IC for active-matrix LCDs, with a proposed iterative charge-sharing based (ICSB) capacitor-string that interpolates two output voltages from a resistor-string DAC. Iterative mode change between a capacitive voltage division mode and a charge sharing mode in the ICSB capacitor-string interpolation suppresses the effect of mismatches between capacitors and that of parasitic capacitances; thus, a highly linear capacitor sub-DAC is realized. In addition, the area-sharing layout technique, which stacks the interpolation capacitor-string on top of the R-DAC area, reduces the driver channel size and extends the bit resolution of the gamma-corrected nonlinear main R-DAC. Consequently, the proposed ICSB capacitor-string interpolation scheme provides highly uniform channel performance by passively dividing the coarse voltages from the global resistor-string DAC with high area efficiency, and more effective bit resolution for nonlinear gamma correction. The prototype column driver IC was implemented using a 0.11-mu m CMOS process. The area occupation of the DAC and buffer amplifier per channel is only 188 x 15 mu m(2), and the static power consumption is 0.9 mu A/channel with no additional static power dissipation for the interpolation. The measured maximum DNL and INL are 0.25 LSB and 0.43 LSB, respectively. The measured maximum inter-channel DVO is 5.6 mV. The proposed chip achieves state-of-the-art performance in terms of chip size and channel-to-channel uniformity.
引用
收藏
页码:766 / 782
页数:17
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