Implementation of a digital signal processor in a DBF self-beam-steering array antenna

We have proposed a digital beamforming (DBF) self-beam-steering array antenna which features maximal ratio combining enabling it to efficiently use the received power or to rapidly track the desired signal. The DBF self-beamsteering array antenna utilizes digital signal processing with an active array antenna configuration. ASIC implementation of the digital signal processor is inevitable for DBF antenna application in practical mobile communications environments. In this paper, we present a scheme for implementing a digital signal processor in ASICs using ten FPGAs (Field Programmable Gate Arrays) for the DBF self-beam-steering array antenna. Results of some experiments obtained in a large radio anechoic chamber are shown to confirm a basic function of the system.