Survey of critical failure events in on-chip interconnect by fault tree analysis

被引：3
|
作者：
Yokogawa, Shinji [1 ]
Kunii, Kyousuke [2 ]
机构：
[1] Univ Electrocommun, Infopowered Energy Syst Res Ctr, Chofu, Tokyo 1828585, Japan
[2] Univ Electrocommun, Grad Sch Informat & Engn, Chofu, Tokyo 1828585, Japan
来源：
JAPANESE JOURNAL OF APPLIED PHYSICS | 2018年 / 57卷 / 07期
关键词：
COPPER INTERCONNECTS; VOID GROWTH; ELECTROMIGRATION; RELIABILITY; RESISTIVITY;
D O I：
10.7567/JJAP.57.07MG01
中图分类号：
O59 [应用物理学];
学科分类号：
摘要：
In this paper, a framework based on reliability physics is proposed for adopting fault tree analysis (FTA) to the on-chip interconnect system of a semiconductor. By integrating expert knowledge and experience regarding the possibilities of failure on basic events, critical issues of on-chip interconnect reliability will be evaluated by FTA. In particular, FTA is used to identify the minimal cut sets with high risk priority. Critical events affecting the on-chip interconnect reliability are identified and discussed from the viewpoint of long-term reliability assessment. The moisture impact is evaluated as an external event. (C) 2018 The Japan Society of Applied Physics
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页数：7
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