DC and RF Performance Optimization of Strained Si/Si1-xGex Heterojunction SOI P-TFET

This paper proposes DC and RF performance optimization of single gate strain Si/Si1-xGex P- channel gate-drain underlap Tunnel Field Effect Transistor (TFET) using 2D TCAD simulation tool. Here, in the heterodielectric gate structure, the ION current is improved by effectively situating the gate over the source edge. Gate-drain underlap structure provides reduced ambipolar conduction in the proposed P-channel Tunnel Field Effect Transistor (P-TFET) device. The proposed device demonstrates great execution with an I-ON/I-OFF of 10(14) and average subthreshold swing (SS) of 53mV/dec. In addition, we have also optimized analog/RF figure of merit characteristics such as parasitic capacitances, transconductance, and transit frequency of the proposed Heterojunction SOI P-TFET (HJ-SOI P-TFET).