Reduced length checking sequences

被引：62

作者：

Hierons, RM ^{[1
]}

Ural, H

机构：

[1] Brunel Univ, Dept Informat Syst & Comp, Uxbridge UB8 3PH, Middx, England

[2] Univ Ottawa, Sch Informat Technol & Engn, Ottawa, ON K1N 6N5, Canada

来源：

IEEE TRANSACTIONS ON COMPUTERS | 2002年 / 51卷 / 09期

基金：

加拿大自然科学与工程研究理事会;

关键词：

finite state machine; checking sequence; test minimization; distinguishing sequence;

D O I：

10.1109/TC.2002.1032630

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Here, the method proposed in [13] for constructing minimal-length checking sequences based on distinguishing sequences is improved. The improvement is based on optimizations of the state recognition sequences and their use in constructing test segments. It is shown that the proposed improvement further reduces the length of checking sequences produced from minimal, completely specified, and deterministic finite state machines.

引用

页码：1111 / 1117

页数：7

共 14 条

[1] AN OPTIMIZATION TECHNIQUE FOR PROTOCOL CONFORMANCE TEST-GENERATION BASED ON UIO SEQUENCES AND RURAL CHINESE POSTMAN TOURS [J].

AHO, AV ;

DAHBURA, AT ;

LEE, D ;

UYAR, MU .

IEEE TRANSACTIONS ON COMMUNICATIONS, 1991, 39 (11) :1604-1615

[2] THE CCITT-SPECIFICATION AND DESCRIPTION LANGUAGE SDL [J].

BELINA, F ;

HOGREFE, D .

COMPUTER NETWORKS AND ISDN SYSTEMS, 1989, 16 (04) :311-341

[3] AN INTRODUCTION TO ESTELLE - A SPECIFICATION LANGUAGE FOR DISTRIBUTED SYSTEMS [J].

BUDKOWSKI, S ;

DEMBINSKI, P .

COMPUTER NETWORKS AND ISDN SYSTEMS, 1987, 14 (01) :3-23

[4] FORMAL METHODS FOR GENERATING PROTOCOL CONFORMANCE TEST SEQUENCES [J].

DAHBURA, AT ;

SABNANI, KK ;

UYAR, MU .

PROCEEDINGS OF THE IEEE, 1990, 78 (08) :1317-1326

[5]

Gill A., 1962, INTRO THEORY FINITE

[6] A METHOD FOR DESIGN OF FAULT DETECTION EXPERIMENTS [J].

GONENC, G .

IEEE TRANSACTIONS ON COMPUTERS, 1970, C 19 (06) :551-+

[7] STATECHARTS - A VISUAL FORMALISM FOR COMPLEX-SYSTEMS [J].

HAREL, D .

SCIENCE OF COMPUTER PROGRAMMING, 1987, 8 (03) :231-&

[8]

Hennie F. C., 1964, P 5 ANN S SWITCH CIR, P95, DOI 10.1109/SWCT.1964.8

[9] TESTING FINITE-STATE MACHINES - STATE IDENTIFICATION AND VERIFICATION [J].

LEE, D ;

YANNAKAKIS, M .

IEEE TRANSACTIONS ON COMPUTERS, 1994, 43 (03) :306-320

[10]

LEE D, 1996, P IEEE, V84, P1089

← 1 2 →