High Performance MRAM-Based Stateful Logic

Static power due to the leakage currents has become a major concern in CMOS logic circuits as the technology is scaled down. Introducing non-volatility into logic circuits is a promising solution offering zero standby power and instant-on applications. Recently, spin-transfer torque magnetoresistive random-access memory (STT-MRAM) circuits have been presented to enable stateful logic by implementing reprogrammable- and implication-based magnetic tunnel junction logic operations. In this work we describe tradeoffs in the design of MRAM-based stateful logic architectures. It has been shown that although the implication logic outperforms the reprogrammable architecture, a combination of these two architectures reduces the number of required logic steps and the energy consumption, however, at the cost of reduced reliability. MRAM-based logic is also well suited for high performance parallel non-volatile computations as it is shown by an example.