A System-level Scheme for Resistance Drift Tolerance of a Multilevel Phase Change Memory

This paper presents a system-level scheme to alleviate the effect of resistance drift in a multilevel phase change memory (PCM) for data integrity. In this paper, novel criteria of separation of the PCM resistance for multilevel cell storage and selection of the threshold resistances between levels are proposed by using a median based method based on a row of PCM cells as reference. The threshold resistances found by the proposed scheme drift with time, thus providing an efficient and viable approach when the number of levels increases. A detailed analysis of the proposed level separation and threshold resistance selection is pursued. The impact of different parameters (such as the write region and the number of cell in a row) is assessed with respect to the generation of the percentage accuracy. The proposed approach results in a substantial improvement in performance compared with existing schemes found in the technical literature.