An N-Path Filter with Multiphase PWM Clocks for Harmonic Response Suppression

被引：0

作者：

Rayudu, Venkata Suresh ^{[1
]}

Kang, Heechai ^{[1
]}

Gharpurey, Ranjit ^{[1
]}

机构：

[1] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA

来源：

2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS) | 2020年

关键词：

Pulse-Width Modulation (PWM); N-path filter; Harmonic Response; FRONT-END;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A switched-capacitor N-path circuit can be employed for filtering an RF signal, as well as a passive downconverter. A known limitation of a switch-based N-path filter is that in addition to downconverting signals around the desired center frequency, the circuit also downconverts signals located around harmonics of the LO frequency. An N-path filter that uses a PWM representation of a sinusoidal LO to mitigate harmonic downconversion is proposed in this work. Single-edge, natural-sampling pulse-width modulated (PWM) clocks are used to drive the switches in the N-path filter. The potential for employing PWM for providing gain control is also described.

引用

页数：4

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