Design a Delay Amplified Digital Aging Sensor Circuit in 65nm CMOS

With the decrease of the transistor feature size, aging phenomena is becoming one key factor affecting the performance of the circuit. Digital measure the performance degradation is one of critical problems in aging adaptive design technique. In this paper, we propose a delay amplified digital (DAD) aging sensor circuit which is combined aging principle with delay amplified circuit. Firstly, a reference delay circuit is designed according to the monitored combinational logic circuit. The reference and combinational logic circuit generate an enable pulse. To improve the measurement accuracy, the enable pulse is amplified by N times by a timing multiplier circuit (TMC). Finally, digital sampling circuit output aging degradation using amplified enable pulse. Under TSMC 65nm CMOS technology, DAD aging sensor circuit is designed. Experimental results show that the precision of aging sensor has a correct function.