Implementation of energy-efficient approximate multiplier with guaranteed worst case relative error

被引:6
作者
Loukrakpam, Merin [1 ,2 ]
Choudhury, Madhuchhanda [1 ]
机构
[1] NIT Silchar, Dept Elect & Commun Engn, Silchar, Assam, India
[2] Manipur Tech Univ, Dept Elect & Commun Engn, Imphal, Manipur, India
来源
MICROELECTRONICS JOURNAL | 2019年 / 88卷
关键词
Approximate computing; Energy efficiency; Error resilience; Multiplier; Piecewise linear approximation; DESIGN;
D O I
10.1016/j.mejo.2019.04.006
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Existing design methods for approximate multipliers typically rely on exhaustive simulation to determine the approximation error. However, this approach is not tractable for complex designs. In this paper, a two-dimensional piecewise linear approximation method for multiplication that formally guarantees the maximum error is proposed. Based on this method, a design procedure to implement energy-efficient approximate multipliers is also proposed. Three 32-bit unsigned approximate multipliers with guaranteed maximum errors of 12.5%, 3.13% and 0.78% were realized using the design procedure. The efficiencies of the proposed designs were evaluated by comparing their parameters with that of the exact and state-of-the-art approximate multipliers. The proposed designs deliver up to 91.8% (62.1%) energy saving when compared with that of exact (approximate) multipliers. The effectiveness of the approximate multipliers was also assessed in an image smoothening application.
引用
收藏
页码:1 / 8
页数:8
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