A Novel Approach to Design Low Power and High Speed Self-Repairing Full Adder Circuit

For industrial application self-checking designs are required which are having complete fault coverage with low power and high speed as functionality of an arithmetic circuit is destroyed if basic full adder circuit is faulty. This error detection and correction completely depends on internal functionality of self-checking and self-repairing circuit. This proposed self-checking and self-repairing full adder circuit consumes low power and high speed when compared to existing circuits. Single and double fault are detected during testing of full adder circuit having transient and permanent fault. Proposed structures subsume lower area overhead relative to traditional structures.