Solving Technical and Economical Barriers to the Adoption of Through-Si-Via 3D Integration Technologies

被引：12

作者：

Beyne, Eric ^{[1
]}

机构：

[1] IMEC, B-3001 Leuven, Belgium

来源：

EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3 | 2008年

关键词：

D O I：

10.1109/EPTC.2008.4763408

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

3D integration technologies using through-Si via (TSV) technologies are receiving increased interest. A wide diversity of technologics is being proposed and an increasing number of potential application areas are identified. Different application domains have different TSV requirements and justify different integration approaches. The most important challenges to a widespread use of 3D integration technologies are related to the economics of the 3D TSV and stacking process, the availability of suitable equipment for large scale production and the possible negative impact on the device quality and reliability of the TSV processing.

引用

页码：29 / 34

页数：6