Enhanced PAiD - An EDA Tool for Asynchronous Circuit Design and Verification

被引：0

作者：

Nguyen, Tin T. ^{[1
]}

Bui, Thang H. ^{[1
]}

Khoi-Nguyen Le-Huu ^{[2
]}

Anh-Vu Dinh-Duc ^{[2
]}

机构：

[1] Ho Chi Minh City Univ Technol, Ho Chi Minh City, Vietnam

[2] Univ Informat Technol, VNUHCM, Minh City, Vietnam

来源：

2014 11TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING/ELECTRONICS, COMPUTER, TELECOMMUNICATIONS AND INFORMATION TECHNOLOGY (ECTI-CON) | 2014年

关键词：

FORMAL VERIFICATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

EDA has been proposed for a long time as a category of reliable software tools for designing electronic systems. Although some of them have been considered as powerful tools for asynchronous circuits - a prominent approach solving the biggest defect of synchronous circuits: clock distribution issue, researches in verifying the correctness of those circuits are still limited. Therefore, an enhanced version of PAiD - an EDA tool that has been developed at HoChiMinh City University of Technology (HCMUT) will be proposed in this work with some case studies. It not only helps engineers design, synthesize but also verify asynchronous circuits. Besides, a good strategy to improve the verifying performance is also discussed.

引用

页数：6