Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p(+)-i-n(+) tunneling junction, the TFET with a gate length of similar to 200 nm exhibits good subthreshold swing of similar to 70 mV/dec, superior drain-induced-barrier-lowering of similar to 17 mV/V, and excellent I-on-I-off ratio of similar to 10(7) with a low I-off (similar to 7 pA/mu m). The obtained 53 mu A/mu m I-on can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.