A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter

被引：2

作者：

Ito, Tomohiko ^{[1
]}

Ueno, Takeshi ^{[1
]}

Kurose, Daisuke ^{[1
]}

Yamaji, Takafumi ^{[1
]}

Itakura, Tetsuro ^{[1
]}

机构：

[1] Toshiba Co Ltd, Ctr Corp Res & Dev, Saiwai Ku, Kawasaki, Kanagawa 2128582, Japan

来源：

IEICE ELECTRONICS EXPRESS | 2005年 / 2卷 / 15期

关键词：

analog-to-digital converter; ADC; low-power design;

D O I：

10.1587/elex.2.429

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The optimum bit/stage configuration is an important issue in the design of a low-power pipeline analog-to-digital converter ( ADC). Prior to this work, power considerations based on a linear-model have been reported [ 1]. In this letter, the slew-rate limitation, a non-linear effect, is taken into consideration in low-power design. In the case of a 10-bit, 200-MSPS ADC using 90-nm CMOS technology, the lowest power bit-arrangement was found to be 1.5 bit/stage. A test chip was fabricated for confirmation, and a power dissipation of 105 mW was achieved.

引用

页码：429 / 433

页数：5

共 13 条

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