IMPROVING MULTISPECTRAL SATELLITE IMAGE COMPRESSION USING ONBOARD SUBPIXEL REGISTRATION

被引:0
作者
Albinet, Mathieu [1 ]
Camarero, Roberto [1 ]
Isnard, Maxime [2 ]
Poulet, Christophe [3 ]
Perret, Jokin [3 ]
机构
[1] CNES, 18 Av Edouard Belin, F-31401 Toulouse 9, France
[2] THALES SERVICES, F-31400 Toulouse, France
[3] EREMS, F-31130 Flourenes, France
来源
SATELLITE DATA COMPRESSION, COMMUNICATIONS, AND PROCESSING IX | 2013年 / 8871卷
关键词
compression; satellite; registration; multispectral; resampling; interpolation; VHDL;
D O I
10.1117/12.2024066
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Future CNES earth observation missions will have to deal with an ever increasing telemetry data rate due to improvements in resolution and addition of spectral bands. Current CNES image compressors implement a discrete wavelet transform (DWT) followed by a bit plane encoding (BPE) but only on a mono spectral basis and do not profit from the multispectral redundancy of the observed scenes. Recent CNES studies have proven a substantial gain on the achievable compression ratio, +20% to +40% on selected scenarios, by implementing a multispectral compression scheme based on a Karhunen Loeve transform (KLT) followed by the classical DWT+BPE. But such results can be achieved only on perfectly registered bands; a default of registration as low as 0.5 pixel ruins all the benefits of multispectral compression. In this work, we first study the possibility to implement a multi-bands subpixel onboard registration based on registration grids generated on-the-fly by the satellite attitude control system and simplified resampling and interpolation techniques. Indeed bands registration is usually performed on ground using sophisticated techniques too computationally intensive for onboard use. This fully quantized algorithm is tuned to meet acceptable registration performances within stringent image quality criteria, with the objective of onboard real-time processing. In a second part, we describe a FPGA implementation developed to evaluate the design complexity and, by extrapolation, the data rate achievable on a space-qualified ASIC. Finally, we present the impact of this approach on the processing chain not only onboard but also on ground and the impacts on the design of the instrument.
引用
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页数:10
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