High-performance of the Multiplication over the Quadratic Extension in Montgomery Domain for the Pairing Cryptosystems

In our paper we propose an architecture to calculate the operation of multiplication over F-p2 in the tower extension field arithmetic for pairing. This tower used in pairings based cryptography. Pairing is becoming the most popular for Public Key Cryptosystems. For the same security level the cryptosystem pairing use much smaller key length than other cryptosystems like RSA. We propose an efficient and optimized architectures that considerably accelerate the calculation of Miller algorithm in pairing-based cryptography. In our architecture we use the Montgomery multiplication based on the systolic architecture published in [17]. We propose an efficient design to implement multiplication over F-p2. In this work our architecture is designed with VHDL in order to use the component flexible DSP of Xilinx FPGAs. This design of multiplication is scalable and depends on the size of words.