An Analysis of the Timing Behavior of CMOS Digital Blocks under Simultaneous Switching Noise Conditions

被引：0

作者：

Azais, F. ^{[1
]}

Bertrand, Y. ^{[1
]}

Renovell, M. ^{[1
]}

机构：

[1] Univ Montpellier 2, LIRMM, CNRS, F-34392 Montpellier, France

来源：

PROCEEDINGS OF THE 2009 IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS | 2009年

关键词：

signal integrity; simulteneous switching noise (SSN); timing behavior; digital circuits;

D O I：

10.1109/DDECS.2009.5012119

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper analyzes the impact of Simultaneous Switching Noise (SSN) on the timing behavior of CMOS digital blocks. The concept of Instantaneous Transfer Function is introduced to interpret noisy signals and perform timing measurements on such signals. It is shown that the average swing during switching is the key parameter to predict the noise impact on the delay of a logic path, whereas the peak of noise is not relevant. The influence of structural parameters such as the block topology is evaluated, and the unpredictable aspect of SSN impact on path delay is highlighted.

引用

页码：158 / 163

页数：6

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