An 80-Gbit/s 1:2 demultiplexer in 10-based HEMT technology

In this paper, we present an 80-Gbit/s 1:2 demultiplexer (DEMUX) that was fabricated using a 0.1-mum-gate-length InP-based HEMT technology. A data input buffer with a common-gate amplifier in front has been employed so as to achieve a low return loss over wide frequency range and to suppress signal distortion, which is mainly caused by multiple reflections between a DEMUX chip and a signal source. A DEMUX core consisting of a D-type flip-flop (FF) and a tri-stage FF assures the edge alignment of two channels of deserialized signals. The 1:2 DEMUX operated at up to 80 Gbit/s, which was limited by our measurement equipment. At that bit-rate, the input sensitivity and clock phase margin estimated from monitoring eye-openings were about 100 mVp-p and 160 degrees, respectively. The skew of the two output signals was only 2 ps.