Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-κ/Metal Gate Stack p-Type Metal-Oxide-Semiconductor Field Effect Transistors

被引：3

作者：

Sato, Motoyuki ^{[1
]}

Aoyama, Takayuki ^{[1
]}

Nara, Yasuo ^{[1
]}

Ohji, Yuzuru ^{[1
]}

机构：

[1] Semicond Leading Edge Technol Inc, Tsukuba, Ibaraki 3058569, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2009年 / 48卷 / 04期

关键词：

MODEL;

D O I：

10.1143/JJAP.48.04C002

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

We have clarified the effects of activation annealing temperature on the negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime improvement of HfSiON/TiN gate stack p-type metal-oxide-semiconductor field effect transistors. Higher-temperature annealing is effective for the improvement in NBTI and TDDB lifetime. This is due to the Si substrate oxidation occuring during the high-temperature annealing, resulting in interface defect state reduction. Annealing is also effective for reducing threshold voltage with consequential improvement in device performance. (C) 2009 The Japan Society of Applied Physics

引用

页数：5

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