共 26 条
[1]
Signal Integrity Design and Analysis of Differential High-Speed Serial Links in Silicon Interposer With Through-Silicon Via
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY,
2019, 9 (01)
:107-121
[2]
England L, 2017, INT EL DEVICES MEET
[4]
Design and Modeling Methodology of Vertical Interconnects for 3DI Applications
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY,
2011, 1 (02)
:163-167
[5]
Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions
[J].
IEEE TRANSACTIONS ON ADVANCED PACKAGING,
2010, 33 (04)
:804-817
[7]
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse
[J].
PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC),
2019,
[8]
High-Frequency Scalable Modeling and Analysis of a Differential Signal Through-Silicon Via
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY,
2014, 4 (04)
:697-707
[9]
High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY,
2011, 1 (02)
:181-195
[10]
Kumar V, 2016, IEEE T ELECTRON DEV, V63, P2503, DOI 10.1109/TED.2016.2556709