A Simulation-based Fault Injection Mechanism of Digital Circuit

被引：5

作者：

Zhou, Quan ^{[1
]}

Yan, Xin ^{[1
]}

Yang, Liang ^{[1
]}

机构：

[1] Xian Microelect Technol Inst, Taibai South Rd, Xian, Shaanxi, Peoples R China

来源：

5TH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTER SCIENCE APPLICATIONS AND TECHNOLOGIES (ACSAT 2017) | 2017年

关键词：

VHDL; test bench; fault-tolerance; reliability design; reliability validation; fault injection;

D O I：

10.23977/acsat.2017.1006

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Fault injection is a key step in the validation of fault-tolerant design. This paper introduces a novel simulation-based fault injection method. The proposed method is implemented directly in Test Bench (TB) by modifying the signal values in VHDL model, and the fault type and ratio, transient fault duration and fault injection rate etc. can be easily adjusted according to requirements. It also supports the random fault injection by giving a random distribution. Compared with existing approaches, this simple method that can be designed and used immediately has a better extendibility and a better tailing capability due to the fact that it is field programmable in TB. Fault injection experiment shows that this approach is flexible and easy to use.

引用

页码：44 / 54

页数：11

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