Subthreshold analytical model for dual- material double gate ferroelectric field effect transistor (DMGFeFET)

被引:5
作者
Mehta, Hema [1 ]
Kaur, Harsupreet [1 ]
机构
[1] Univ Delhi, Dept Elect Sci, South Campus, New Delhi, India
关键词
analytical modeling; dual-material (DM); double gate; ferroelectric (FE); short channel effects; SOI MOSFET; CAPACITANCE; CMOS;
D O I
10.1088/1361-6641/ab194d
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, an analytical model for dual-material double gate ferroelectric field effect transistor (DMGFeFET) has been developed to investigate the impact of dual-material gate (DMG) and ferroelectric insulator on electrostatic integrity of the device. Landau-Khalatnikov equation along with Poisson's equation has been used to obtain various parameters such as potential profile distribution, threshold voltage roll-off, drain induced barrier lowering, subthreshold slope etc. The results obtained have been comprehensively compared with equivalent dual-material double gate FET (DMGEL,T) and it has been demonstrated that DMGFeFET leads to significant improvement in gate controllability as well as substantial reduction in DIBL values. Furthermore, the proposed device exhibits reduction in subthreshold current by 3 orders as compared to conventional DMGEL,T, thereby implying reduced static power dissipation and efficient device operation. The results obtained using developed model have been validated by numerical simulation results obtained by ATLAS Silvaco tool.
引用
收藏
页数:9
相关论文
共 31 条
  • [1] Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved IOFF Sensitivity in Presence of Parasitic Capacitance
    Agarwal, Harshit
    Kushwaha, Pragya
    Duarte, Juan Pablo
    Lin, Yen-Kai
    Sachid, Angada B.
    Chang, Huan-Lin
    Salahuddin, Sayeef
    Hu, Chenming
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (03) : 1211 - 1216
  • [2] Evaluation of Si:HfO2 Ferroelectric Properties in MFM and MFIS Structures
    Anderson, Jackson D.
    Merkel, Jordan
    Macmahon, David
    Kurinec, Santosh K.
    [J]. IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 6 (01): : 525 - 534
  • [3] [Anonymous], 2014, ATLAS USER MANUAL SI
  • [4] Design challenges of technology scaling
    Borkar, S
    [J]. IEEE MICRO, 1999, 19 (04) : 23 - 29
  • [5] Energy barriers, demons, and minimum energy operation of electronic devices
    Cavin, RK
    Zhirnov, VV
    Hutchby, JA
    Bourianoff, GI
    [J]. FLUCTUATION AND NOISE LETTERS, 2005, 5 (04): : C29 - C38
  • [6] Channel doping-dependent analytical model for symmetric double gate metal-oxide-semiconductor field-effect transistor. I. Extraction of subthreshold characteristics
    Cho, Edward Namkyu
    Shin, Yong Hyeon
    Yun, Ilgu
    [J]. JOURNAL OF APPLIED PHYSICS, 2013, 113 (21)
  • [7] Device scaling limits of Si MOSFETs and their application dependencies
    Frank, DJ
    Dennard, RH
    Nowak, E
    Solomon, PM
    Taur, Y
    Wong, HSP
    [J]. PROCEEDINGS OF THE IEEE, 2001, 89 (03) : 259 - 288
  • [8] 2-D Analytical Modeling of Threshold Voltage for Graded-Channel Dual-Material Double-Gate MOSFETs
    Goel, Ekta
    Kumar, Sanjay
    Singh, Kunal
    Singh, Balraj
    Kumar, Mirgender
    Jit, Satyabrata
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (03) : 966 - 973
  • [9] Holmes G.C., 2002, Math. Gazette, V86, P473, DOI DOI 10.2307/3621149
  • [10] Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics
    Khandelwal, Sourabh
    Duarte, Juan Pablo
    Khan, Asif Islam
    Salahuddin, Sayeef
    Hu, Chenming
    [J]. IEEE ELECTRON DEVICE LETTERS, 2017, 38 (01) : 142 - 144