A Study of a Fault-tolerant System Using Dynamic Partial Reconfiguration

被引：1

作者：

Ogido, Seiya ^{[1
]}

Yamada, Chikatoshi ^{[1
]}

Miyagi, Kei ^{[1
]}

Ichikawa, Shuichi ^{[2
]}

机构：

[1] Okinawa Coll, Natl Inst Technol, 905 Henoko, Nago, Okinawa, Japan

[2] Toyohashi Univ Technol, 1-1 Hibarigaoka,Tempaku Cho, Toyohashi, Aichi, Japan

来源：

2017 FIFTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR) | 2017年

关键词：

D O I：

10.1109/CANDAR.2017.57

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose reconfigurable fault tolerant architecture which can recovery from failure status with spare space. Generally, embedded processors are required to need high reliability. In particular, tile structure which is the key of the architecture for the reconfigurable device. We propose reconstruction for circuits by using the Tcl script. The proposed method is kept the reliability by redundant of circuit. We discuss trade-off for implementation using Xilinx FPGAs.

引用

页码：600 / 602

页数：3

共 10 条

[1]

Amagasaki M., 2013, P FPL

[2]

AMAGASAKI Motoki, 2013, IEICE T D, V96, P3019

[3]

[Anonymous], 2015, VIV DES SUIT TUT PAR

[4]

DeHon Andr, 2013, P FPT

[5]

FUJISAWA Kentaro, 2014, IEICE TECHNICAL REPO, V114, P13

[6] An Easily Testable Routing Architecture and Prototype Chip [J].

Inoue, Kazuki ;

Koga, Masahiro ;

Amagasaki, Motoki ;

Iida, Masahiro ;

Ichida, Yoshinobu ;

Saji, Mitsuro ;

Iida, Jun ;

Sueyoshi, Toshinori .

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2012, E95D (02) :303-313

[7]

Kawai H., 2006, P RECONFIG 2006, P198

[8]

Lakamraju V., 2000, P FPGA

[9]

Okada T., 2010, IEICE TECHNICAL REPO, V110, P33

[10]

Xilinx Inc, 2015, VIV DES SUIT US GUID

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