Modeling Methodologies for Multi Level PCB-Package Co-Simulation & Co-Design

被引:0
|
作者
Scogna, Antonio Ciccomancini [1 ]
Chiang, ChunTong [2 ]
Lau, Linus [3 ]
机构
[1] CST Amer Inc, 492 Old Connecticut Path,505, Framingham, MA 01701 USA
[2] CST S E Asia, Singapore, Singapore
[3] CST, Kepong, Malaysia
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
引用
收藏
页码:57 / 57
页数:1
相关论文
共 50 条
  • [41] CHIP-PKG-PCB Co-Design Methodology
    Sato, Atsushi
    Kimura, Yoshiyuki
    Matsumura, Motoaki
    FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 2013, 49 (01): : 131 - 137
  • [42] Chip-Package Thermal Co-Simulation Technique for Thermally Aware Chip Design
    Karimanal, Kamal
    2010 12TH IEEE INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONIC SYSTEMS, 2010,
  • [43] Design and Application of a Domain Specific Modeling Language for Distributed Co-Simulation
    Krammer, Martin
    Benedikt, Martin
    2019 IEEE 17TH INTERNATIONAL CONFERENCE ON INDUSTRIAL INFORMATICS (INDIN), 2019, : 677 - 682
  • [44] ESD Co-Design methodologies for RF and mmW circuits
    Berenguer, Roc
    2014 10TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME 2014), 2014,
  • [45] Package-silicon co-design - Experiment with an SOC design
    Suresh, PR
    Sundararajan, PK
    Goel, A
    Udayakumar, H
    Srinivasan, C
    Sinari, V
    Ravinutala, R
    17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 531 - 536
  • [46] Thirty Years of Research and Methodologies in Value Co-Creation and Co-Design
    Avila-Garzon, Cecilia
    Bacca-Acosta, Jorge
    SUSTAINABILITY, 2024, 16 (06)
  • [47] IC-Package Co-design by Computational Thermographics
    2013 8TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2013, : 170 - 171
  • [48] Co-Design of Interchiplet, Package, and System Interconnect Protocols
    Carusone, Tony Chan
    Dunwell, Dustin
    Gupta, Sundeep
    Giuliano, Letizia
    Auge, Adrien
    Klempa, Michael
    Fung, Sue Hung
    IEEE MICRO, 2025, 45 (01) : 35 - 40
  • [49] Chip and package co-design technique for clock networks
    Zhu, Q
    Dai, WWM
    1996 IEEE MULTI-CHIP MODULE CONFERENCE, PROCEEDINGS, 1996, : 160 - 163
  • [50] New CAD strategies for IC/package co-design
    Nguyen, L
    Maher, MA
    1999 INTERNATIONAL CONFERENCE ON HIGH DENSITY PACKAGING AND MCMS, PROCEEDINGS, 1999, 3830 : 137 - 141