Impact of CMOS Post Nitridation Annealing on Reliability of 40nm 512kB Embedded Flash Array

被引：0

作者：

Kempf, Thibault ^{[1
,2
,3
]}

Mantelli, Marc ^{[1
]}

Maugain, Francois ^{[1
]}

Regnier, Arnaud ^{[1
]}

Portal, Jean-Michel ^{[2
]}

Masson, Pascal ^{[3
]}

Moragues, Jean-Michel ^{[1
]}

Hesse, Marjorie ^{[1
,3
]}

della Marca, Vincenzo ^{[2
]}

Julien, Franck ^{[1
]}

Niel, Stephan ^{[1
]}

机构：

[1] STMicroelectronics, Rousset, France

[2] Aix Marseille Univ, IM2NP, Marseille, France

[3] Nice Sophia Antipolis Univ, EpOC, Biot, France

来源：

2017 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP (IIRW) | 2017年

关键词：

40nm Flash NOR; embedded process; circuit testing; nitrided oxide; fixed charge; oxide wearout; data retention; endurance; on-chip characterization; MEMORY; OXYNITRIDE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.

引用

页码：45 / 50

页数：6

共 5 条

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