An FPGA 2D-convolution unit based on the CAPH language

Convolution is an important operation in image processing applications, such as edge detection, sharpening and adding blurring. Convolving video streams in real time is a challenging task for PC systems, however, FPGA devices can successfully be used in these tasks. In this article, the design and implementation of a reconfigurable FPGA architecture for 2D-convolution filtering is described. The filtered frames are calculated at a rate of 103 frames per second for images up to 1200 x 720 pixel resolution. Using a shift-based arithmetic and circular buffers, the developed FPGA architecture allows to reduce the hardware resource consumption up to 98% compared to the conventional convolution implementations, provides high speed processing and enables to manage large number of different convolution kernels. On the other hand, using the CAPH language, it is possible to reduce the design time up to 75% compared to the plain VHDL design. Furthermore, to maintain high flexibility in concordance with the input video, the developed hardware allows to configure the resolution of the input images with values of 3 x Y up to 1200 x Y, and allows scalability for different sizes of convolution kernels of simple and systematic form. Finally, the developed FPGA architecture for the proposed method was implemented and validated in an FPGA Cyclone II EP2C35F672C6 embedded in an Altera development board DE2.