Low-power and Real-time Computer Vision On-chip

被引：0

作者：

Pang, Wei ^{[1
]}

Huang, Hantao ^{[2
]}

An, Fengwei ^{[3
]}

Yu, Hao ^{[1
,2
]}

机构：

[1] Southeast Univ, Natl ASIC Syst Engn Res Ctr, Nanjing 210096, Jiangsu, Peoples R China

[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore

[3] Hiroshima Univ, Higashihiroshima, Japan

来源：

2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2016年

关键词：

computer vision; recognition coprocessor; face recognition accelerator; real-time;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Computer vision on chip is critical for many emerging applications such as advanced driver assistance system (ADAS), which requires a low-power and real-time image data analytics. Therefore, designing a computer-vision accelerator on-chip to achieve high throughput as well as low power is greatly needed. This paper reviews how to have ASIC realization of standard computer vision algorithms such as SIFT/SURF. The first work is a feature-based recognition co-processor with peak power consumption of 31.5mW for real-time recognition of VGA images. The second work is a face recognition accelerator with 23mW for 5.5 frame/s HD images.

引用

页码：43 / 44

页数：2

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