On the design of fast, easily testable ALU's

被引：4
作者：
Blanton, RD [1 ]
Hayes, JP
机构：
[1] Carnegie Mellon Univ, Elect & Comp Dept, Pittsburgh, PA 15213 USA
[2] Univ Michigan, Dept Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2000年 / 8卷 / 02期
关键词：
ALU design; functional faults; regular circuits; testability;
D O I：
10.1109/92.831442
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A design methodology for implementing fast, easily testable arithmetic logic units (ALU's) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either theta(N) complexity (Lin-testable) or theta(1) complexity (C-testable), where N is the input operand size of the ALU, The various levels of testability are achieved by exploiting some inherent properties of carry-lookahead addition. The Lin-testable and C-testable ALU designs require only one extra input, regardless of the size of the ALU. The area overhead for a high-speed 64-bit Lin-testable ALU is only 0.5%.
引用
收藏
页码：220 / 223
页数：4
相关论文
共 16 条
[1]  
Abramovici M, 1990, DIGITAL SYSTEMS TEST
[2]   EFFICIENT TESTING OF OPTIMAL TIME ADDERS [J].
BECKER, B .
IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (09) :1113-1121
[3]  
BLANTON RC, 1995, THESIS U MICHIGAN
[4]   Properties of the input pattern fault model [J].
Blanton, RD ;
Hayes, JP .
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1997, :372-380
[5]   Design of a fast, easily testable ALU [J].
Blanton, RD ;
Hayes, JP .
14TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1996, :9-16
[6]   Testability of convergent tree circuits [J].
Blanton, RDS ;
Hayes, JP .
IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (08) :950-963
[7]  
CHENG W, 1984, P 14 INT S FAULT TOL, P10
[8]  
ELHUNI H, 1986, P 1986 INT TEST C SE, P1024
[9]   EASILY TESTABLE ITERATIVE SYSTEMS [J].
FRIEDMAN, AD .
IEEE TRANSACTIONS ON COMPUTERS, 1973, C 22 (12) :1061-1064
[10]  
KAUTZ WH, 1967, P 8 ANN S SWITCH AUT, P161
12