A 21.2 μA ΔΣ-Based Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

被引:2
作者
Paavola, Matti [1 ]
Kamarainen, Mika [1 ]
Laulainen, Erkka [1 ]
Saukoski, Mikko [1 ]
Koskinen, Lauri [1 ]
Kosunen, Marko [1 ]
Halonen, Kari [1 ]
机构
[1] Aalto Univ, SMARAD Elect Circuit Design Lab 2, FIN-02150 Espoo, Finland
来源
2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE | 2008年
关键词
D O I
10.1109/ASSCC.2008.4708739
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer implemented in a 0.25 -mu m CMOS process is presented. The fully-integrated sensor interface consists of a Delta Sigma sensor front-end that converts the acceleration signal into the digital domain, a decimator, a frequency reference, a clock generator for the front-end, a voltage and current reference, the required reference buffers, and low-dropout regulators (LDOs) needed for system-on-chip power management. The interface IC provides operating modes for 1 and 25 Hz signal bandwidths. The chip with a 1.72 mm(2) active area draws 21.2 mu A in 1 Hz mode, and 97.6 mu A in 25 Hz mode, from a 1.2 - 2.75 V supply. In 1 Hz mode with a +/- 2-g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 1080, 1165 and 930 mu g/root Hz, respectively.
引用
收藏
页码:101 / 104
页数:4
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