Comments on "High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits"

被引：1

作者：

Etiemble, Daniel ^{[1
]}

机构：

[1] Paris Saclay Univ, Lab Comp Sci LRI, F-91940 St Aubin, France

来源：

IEEE ACCESS | 2020年 / 8卷

关键词：

Adders; Transistors; Logic gates; Inverters; Flash memories; CNTFETs; Standards;

D O I：

10.1109/ACCESS.2020.3041531

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In the above article [1], R. A. Jaber et al. present the designs of ternary logic circuits based on CNTFET technology. The motivation for designing ternary gates is based on the following assumption quoted in the abstract: "Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption."

引用

页码：220015 / 220016

页数：2

共 32 条

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