Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

In this paper, electrical characteristics of dual-gate polycrystalline silicon (poly-Si) thin film transistors (TFTs) with different undoped region (UR) offsets are investigated. Performance degradation of the poly-Si TFT is dependent on the offset value, offset direction, and offset location. In addition, the degradation is also dependent on the applied drain bias. Significant performance deterioration is observed when the offset is larger than +/- 0.4 mu m. Even an offset in an individual UR can cause the degradation. At a low drain bias of -0.1 V, the degradation is independent on the direction and the location of the offset. When the drain bias increases to -10 V, the performance degradation of the TFT with the positive UR offset significantly reduces. The physical mechanisms underlying the performance variation are studied by analyzing the energy band diagrams, carrier concentration distributions, and electric field distributions.