A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers

被引：27

作者：

Boo, Hyun H. ^{[1
]}

Boning, Duane S. ^{[1
]}

Lee, Hae-Seung ^{[1
]}

机构：

[1] MIT, Cambridge, MA 02139 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2015年 / 50卷 / 12期

关键词：

Analog-to-digital converter; op-amp; pipelined ADC; reference buffer; switched-capacitor circuits; virtual ground reference buffer; FLIPPED VOLTAGE FOLLOWER; CMOS ADC; AMPLIFIERS;

D O I：

10.1109/JSSC.2015.2467183

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unity-gain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12 b pipelined ADC is implemented in 65 nm CMOS that achieves 67.0 dB SNDR at 250 MS/s and consumes 49.7 mW of power from a 1.2 V power supply.

引用

页码：2912 / 2921

页数：10

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