Building a verification test plan: Trading brute force for finesse

被引：1

作者：

Bacchini, Francine ^{[1
]}

Malik, Sharad ^{[2
]}

Bergeron, Janick ^{[3
]}

Foster, Harry ^{[4
]}

Piziali, Andrew ^{[5
]}

Mitra, Raj Shekher ^{[6
]}

Ahlschlager, Catherine ^{[7
]}

Stein, Doron ^{[8
]}

机构：

[1] Francine Bacchini Inc, San Jose, CA 95120 USA

[2] Princeton Univ, Princeton, NJ 08544 USA

[3] Synopsys, Ottawa, ON, Canada

[4] Mentor Graph Corp, Dallas, TX USA

[5] Cadence Design Syst, Parker, TX USA

[6] Texas Instruments Inc, Bangalore, Karnataka, India

[7] Sun Microsyst, Sunnyvale, CA USA

[8] Cisco Syst Inc, Netanya, Israel

来源：

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 | 2006年

关键词：

design; verification; design verification; verification test plan; functional simulation; formal verification; coverage;

D O I：

10.1109/DAC.2006.229328

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：805 / +

页数：2

共 3 条