±0.5V∼ ±1.5V VHFCMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme

被引：0
|
作者：
Li, SC [1 ]
Cha, JC [1 ]
机构：
[1] Natl Yunlin Univ Sci & Technol, Dept Human & Sci, ATIS Lab, Touliu 640, Taiwan
来源：
ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2002年
关键词：
analog multiplier; modified bridged-triode scheme (MBTS);
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. It brings in the benefits in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The fabricated chip in TSMC 0.35mum n-well SPQM CMOS technology has a nonlinearity error less than 0.8% over +/-0.5V input range under a nominal supply voltage of +/-1.5V, and consumes the total power dissipation of 2.7 mW only.
引用
收藏
页码：227 / 232
页数：6
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