Analysis of scalability of high-performance 3D image processing platform for virtual colonoscopy

被引:0
作者
Yoshida, Hiroyuki [1 ,2 ]
Wu, Yin
Cai, Wenli
机构
[1] Massachusetts Gen Hosp, 3D Imaging Res, Dept Radiol, 25 New Chardon St,Suite 400C, Boston, MA 02114 USA
[2] Massachusetts Gen Hosp, Harvard Med Sch, Boston, MA 02114 USA
来源
MEDICAL IMAGING 2014: PACS AND IMAGING INFORMATICS: NEXT GENERATION AND INNOVATIONS | 2014年 / 9039卷
基金
美国国家卫生研究院;
关键词
3D imaging processing; high-performance computing; performance scalability; virtual colonoscopy;
D O I
10.1117/12.2043869
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
One of the key challenges in three-dimensional (3D) medical imaging is to enable the fast turn-around time, which is often required for interactive or real-time response. This inevitably requires not only high computational power but also high memory bandwidth due to the massive amount of data that need to be processed. For this purpose, we previously developed a software platform for high-performance 3D medical image processing, called HPC 3D-MIP platform, which employs increasingly available and affordable commodity computing systems such as the multicore, cluster, and cloud computing systems. To achieve scalable high-performance computing, the platform employed size-adaptive, distributable block volumes as a core data structure for efficient parallelization of a wide range of 3D-MIP algorithms, supported task scheduling for efficient load distribution and balancing, and consisted of a layered parallel software libraries that allow image processing applications to share the common functionalities. We evaluated the performance of the HPC 3D-MIP platform by applying it to computationally intensive processes in virtual colonoscopy. Experimental results showed a 12-fold performance improvement on a workstation with 12-core CPUs over the original sequential implementation of the processes, indicating the efficiency of the platform. Analysis of performance scalability based on the Amdahl's law for symmetric multicore chips showed the potential of a high performance scalability of the HPC 3D-MIP platform when a larger number of cores is available.
引用
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页数:6
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