A grinding-based manufacturing method for silicon wafers: Generation mechanisms of central bumps on ground wafers

Most integrated circuits (IC) are fabricated using silicon wafers. The continuing shrinkage of the size of IC features has imposed more and more stringent requirements on the wafer flatness. Furthermore, wafer manufacturers are under constant pressure to reduce the wafer cost. The traditional lapping-based manufacturing method is unable to satisfy the ever-increasing demand for better flatness and lower cost. Previous experimental study of a grinding-based manufacturing method has shown that excellent site flatness can be obtained on ground wafers except for a few sites at the wafer center. One cause for the poor flatness at the wafer center is the central bumps on the ground wafers. As a follow-up, this paper investigates the generation mechanisms of the central bumps on ground wafers, and provides solutions to eliminate or reduce them. The understanding and knowledge gained through this study can also be applied to the manufacturing of other semiconductor wafers ( such as germanium, gallium arsenide, and silicon carbide).