A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS

被引：2

作者：

Gope, D ^{[1
]}

Chakraborty, S ^{[1
]}

Jandhyala, V ^{[1
]}

机构：

[1] Univ Washington, Dept Elect Engn, Seattle, WA 98195 USA

来源：

41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004 | 2004年

关键词：

parasitics; multilevel; low-rank; conductors and dielectrics;

D O I：

10.1145/996566.996780

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Parasitic parameter extraction is a crucial issue in Integrated Circuit design. Integral equation based solvers, which guarantee high accuracy, suffer from a time and memory bottleneck arising from the dense matrices generated. In this paper we present a hybrid FMM-QR algorithm that combines the best features of the Fast Multipole Method and the OR based matrix compression method to achieve faster setup and solve time and lower memory requirements. The method is applied to extract parasitic capacitances from the layout of arbitrarily shaped conductors and dielectrics. Examples demonstrating the accuracy and the superior time and memory performances as compared to existing solvers are also presented.

引用

页码：794 / 799

页数：6

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