High Performance 4.5-nm-Thick Compressively-Strained Ge-on-Insulator pMOSFETs Fabricated by Ge Condensation with Optimized Temperature Control

被引:0
作者
Kim, W. -K. [1 ]
Takenaka, M. [1 ]
Takagi, S. [1 ]
机构
[1] Univ Tokyo, Dept Elect Engn & Informat Syst, Bunkyo Ku, 7-3-1 Hongo, Tokyo 1138656, Japan
来源
2017 SYMPOSIUM ON VLSI TECHNOLOGY | 2017年
关键词
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中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We report high performance extremely-thin-body (ETB) Ge-on-Insulator (GOI) pMOSFETs fabricated by a new Ge condensation process with minimized temperature cycles and slow cooling-down rate. This new condensation process effectively suppresses strain relaxation during Ge condensation and creates high compressive strain. By combining the highly-strained GOI substrates with a digital etching process, we successfully realized 4.5-nm-thick strained-GOI pMOSFETs with excellent GOI thickness uniformity. The MOSFETs exhibit highest hole mobility of 138 cm(2)/Vs in GOI thickness less than 5 nm and the hole mobility enhancement of 2.0 over that of best performance GOI pMOSFETs in this thickness range.
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页码:T124 / T125
页数:2
相关论文
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