Analogue CMOS vector normalisation circuit

被引：3

作者：

Fikos, G ^{[1
]}

Siskos, S ^{[1
]}

机构：

[1] Aristotelian Univ Salonika, Dept Phys, Elect Lab, GR-54006 Salonika, Greece

来源：

ELECTRONICS LETTERS | 1999年 / 35卷 / 25期

关键词：

D O I：

10.1049/el:19991503

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel CMOS analogue circuit is proposed, which can be used to perform vector normalisation with respect to a Euclidean measure, with a bias circuit for all inputs and only four transistors per input. It is very fast, with < 1% linearity error over a decade of the norm of the input vector.

引用

页码：2197 / 2198

页数：2

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