Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing

Minimizing power consumption is one of the most important objectives in VLSI design. This paper introduces a methodology for the optimization of total power consumption of template based asynchronous circuits via dual V(dd) assignment, dual V(th) assignment and template sizing while maintaining performance requirements. The utilized circuit model is a Timed Petri-Net which captures the dynamic behavior of the circuit. These three power reduction techniques are properly encoded in a quantum genetic algorithm and evaluated simultaneously. Experimental results are given for a number of 65 nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty. From the experimental results, we show that the combination of asynchronous design and three low power techniques is an effective way to achieve low power and high performance circuits.