BUILDING MANY-CORE PROCESSOR-TO-DRAM NETWORKS WITH MONOLITHIC CMOS SILICON PHOTONICS

被引：149

作者：

Batten, Christopher ^{[1
,2
]}

Joshi, Ajay ^{[3
]}

Orcutt, Jason ^{[2
]}

Khilo, Anatol ^{[2
]}

Moss, Benjamin ^{[2
]}

Holzwarth, Charles W. ^{[4
]}

Popovic, Milos A. ^{[3
]}

Li, Hanqing ^{[5
]}

Smith, Henry I. ^{[2
]}

Hoyt, Judy L. ^{[2
]}

Kaertner, Franz X. ^{[2
]}

Ram, Rajeev J. ^{[2
]}

Stojanovic, Vladimir ^{[2
]}

Asanovic, Krste ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94704 USA

[2] MIT, Dept Elect Engn & Comp Sci, Cambridge, MA 02139 USA

[3] MIT, Elect Res Lab, Cambridge, MA 02139 USA

[4] MIT, Dept Mat Sci & Engn, Cambridge, MA 02139 USA

[5] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA

来源：

IEEE MICRO | 2009年 / 29卷 / 04期

关键词：

INTERCONNECTS; COMPACT;

D O I：

10.1109/MM.2009.60

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

SILICON PHOTONICS IS A PROMISING TECHNOLOGY FOR ADDRESSING MEMORY BANDWIDTH LIMITATIONS IN FUTURE MANY-CORE PROCESSORS. THIS ARTICLE FIRST INTRODUCES A NEW MONOLITHIC SILICON-PHOTONIC TECHNOLOGY, WHICH USES A STANDARD BULK CMOS PROCESS TO REDUCE COSTS AND IMPROVE ENERGY EFFICIENCY, AND THEN EXPLORES THE LOGICAL AND PHYSICAL IMPLICATIONS OF LEVERAGING THIS TECHNOLOGY IN PROCESS OR-TO-MEMORY NETWORKS.

引用

页码：8 / 21

页数：14

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