0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability

被引：1

作者：

Kikukawa, H ^{[1
]}

Tomishima, S

Tsuji, T

Kawasaki, T

Sakamoto, S

Ishikawa, M

Abe, W

Tanizaki, H

Kato, H

Uchikoba, T

Inokuchi, T

Senoh, M

Fukushima, Y

Niiro, M

Maruta, M

Shibayama, A

Ooishi, T

Takahashi, K

Hidaka, H

机构：

[1] Matsushita Elect Ind Co Ltd, Adv LSI Technol Dev Ctr, Semicond Co, Kyoto 6178520, Japan

[2] Mitsubishi Electr Corp, Itami, Hyogo 6648641, Japan

[3] Mitsubishi Elect Engn Co Ltd, Itami, Hyogo 6648641, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2002年 / 37卷 / 07期

关键词：

DRAM; embedded; redundancy; SOC; system LSI; test;

D O I：

10.1109/JSSC.2002.1015693

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-mum triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm(2) and cell efficiency of 51.3% for the 32-Mb capacity, and core size of 33.4 mm(2) and cell efficiency of 58.1% for the 64-Mb capacity are realized. This core can achieve 230-MHz burst access at 1.0-V power-supply condition by adopting a new data bus architecture: merged shift column redundancy. We implemented four test functions to improve the testability of the embedded DRAM core. It realizes the DRAM core test in a logic test environment.

引用

页码：932 / 940

页数：9