Energy-efficient approximate adders for DSP applications

被引：5

作者：

Tirupathireddy, Anubothula ^{[1
]}

Sarada, Musala ^{[1
]}

Srinivasulu, Avireni ^{[2
]}

机构：

[1] Deemed Univ, Dept Elect & Commun Engn, Vignans Fdn Sci Technol & Res, Guntur, Andhra Pradesh, India

[2] JECRC Univ, Dept Elect & Commun Engn, Jaipur, Rajasthan, India

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2021年 / 107卷 / 03期

关键词：

DSP processors; Approximate computing; PDP and CMOS technology; RELIABILITY; POWER;

D O I：

10.1007/s10470-020-01768-w

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, approximate adders were proposed for DSP processors. DSP processors are mainly composed of adders and multipliers at bottom level. The power is minimized in transistor level design. Proposed adders have less power dissipation when compared to existing approximate adders. Results have shown that the proposed adders have less PDP with more accuracy. The circuits were simulated in Cadence virtuoso tool under 45 nm CMOS technology. Supply voltage is + 0.5 V.

引用

页码：649 / 657

页数：9

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