Clock duty cycle adjuster circuit for switched capacitor circuits

被引：13

作者：

Karthikeyan, S ^{[1
]}

机构：

[1] Texas Instruments Inc, Dallas, TX 75243 USA

来源：

ELECTRONICS LETTERS | 2002年 / 38卷 / 18期

关键词：

Clock duty cycle adjuster circuit - Frequency to voltage converter - Pipelined data converters - Pulse width locked loop - Pulsed width detector - Switched capacitor circuits - Voltage controlled delay lines;

D O I：

10.1049/el:20020657

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A pulse width locked loop, which can be used to generate an output clock with a wide range of duty cycle (25 to 75%) precisely, from a single-ended input clock with any duty cycle (25 to 75%) is explained. Measurement results of an application of this loop, in pipelined data converters, are reported.

引用

页码：1008 / 1009

页数：2